Ann: Full Year Statutory Accounts, page-2

Here's the interesting part:

AUDIO PIXELS HOLDINGS LIMITED ACN 094 384 273
DIRECTORS’ REPORT (CONTINUED) Review of operations

During the reporting period there were no significant changes in the nature of the company’s principal activities which were predominately focused on the refinement of the fabrication processes required to mass produce a commercial version of the Company’s proven ground-breaking Micro Electro Mechanical Structures (“MEMS”) based digital loudspeaker.
Audio Pixels is a world leader in the digital transformation of sound reproduction; combining the emergence of a multibillion-dollar MEMS device industry together with the multibillion-dollar loudspeaker market that has over the course of a century become an indispensable fixture of daily life throughout a myriad of industries and applications.
The Company’s primary efforts remained focused on commercialising its ground-breaking MEMS based digital sound wave transducer platform into an industry compliant microchip that will propel audio loudspeakers, systems and ultrasonic sensors from their century old analog origins into the advanced digital era of today.
During this reporting period the Company received MEMS wafers that had already undergone a previous announced refinement of the device’s “dissipation layers”. The refinements implemented to layers that come into contact with each other during normal operation, were based on results attained from a comprehensive research program aimed at delivering practical solutions for the rather unique operational requirements of our MEMS devices.
As was announced (6 December 2017) these wafers failed to meet a very basic electrical specification, which was ultimately traced to faulty manufacturing processes used to fabricate the internal electrical interconnects of the device. The interconnects (often referred to as “through-silicon via” or TSV’s), provide the electrical interconnections between different layers of the chip. The faulty process introduced an imperfection in the interconnect that degraded the device’s internal current flow which adversely increased the time it takes for the device to react to the input signals.
Upon discovery the vendor immediately identified and rectified the defective process which they then definitively proved through a number of rapid trial runs. At the same time the vendor launched and fast tracked a new fabrication run of wafers that meet the required specifications. Reflective of the vendor’s resolute commitment to ensure the successful completion of the fabrication development processes, the vendor instituted an unprecedented number of additional verification points throughout the fabrication process. At each such check point wafers are randomly selected and removed and exhaustively tested for compliance by the vendor, the Company, and in some cases third parties’ experts. So far, all testing conducted including the recently delivered wafers containing “half structures” have all validated and verified that the current fabrication run measurements adhere to our precise specifications. These include specifications pertaining to the newly optimised dissipation layers and electrical interconnects. This was announced to ASX on 26 February 2018.
As was also announced, the Company undertook an exploratory effort to try and develop a method that might repair the electrical properties of the previously received wafers. Utilising highly unconventional techniques the Company managed to rectify individual interconnects, which allowed the combined teams to substantiate that the degradation of the device’s internal current flow was directly attributed to (and limited to) the electrical interconnects. The team’s attention has since been focused on trying to evolve the intricate techniques used to repair individual interconnects into a workable process that is able to address the many interconnects of a single chip. Despite many associated challenges, the team continues this “rectification effort” at least until such time that the Company receives the newly fabricated wafers from its vendors.
Maturing a reliable manufacturing process for any MEMS device let alone a revolutionary device such as ours, makes it near impossible to accurately predict how long it will take to resolve all the challenges, or even predict if new ones might arise. That being said the progress and unwavering commitment of the Company and its vendor to achieve the Company’s mass production requirements are certainly bearing noteworthy results. Among others this is evident by the dramatic reduction in the length of time it now takes to go from start-to-finish of the MEMS fabrication process. The ever-shrinking timeline substantiates the fact that the overwhelming majority of production steps required to fabricate our MEMS chip have been completed and refined into reliable mass manufacturing processes.
The vendor further advises that delivery of the newly fabricated wafers remains on track with their previous advised delivery timelines (as stated in the 6 December 2018 Announcement), whereby they anticipate beginning to deliver the newly fabricated wafers on or about the end of Q1-2018.
Throughput the period the Company continued to refine the capabilities of its ASIC, electronic controls, software algorithms, the chip assembly and packaging process as well as our proprietary measurement systems. To better cope with the receipt of what are expected to be fully functioning wafers and the ensuing demonstration and introduction phases, management has been actively seeking to expand its engineering workforce. Management continues to maintain very active communications with its ever-growing pool of future customers, ranging from industry conglomerates to start-ups wanting to utilise our devices for a wide range of new and fascinating applications.
The Company continues to expand it intellectual property portfolio, now standing at 32 applications with 102 patents granted in various global jurisdictions. Additionally, during the reporting period two additional applications have been drafted for submission to the applicable patent offices.